e EDPS Program
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EDPS 2017 Symposium and Workshop on
Efficient Design and Manufacturing
Tentative Program



Thursday, September 21st, 2017

8:00AM: Breakfast, Registration and Networking
Welcome and Introduction Shishpal Rawat
Session Chair

Shishpal Rawat

President

CEDA

8:45AM: Welcome and Introduction - General Chair

(Please see Presentation)

Dave Anderson

President

SEMI Americas

SEMI Welcoming Remarks

Antun Domic

Chief Technical Officer

Synopsys

9:00AM: Opening Keynote: Some Implications brought in by the Coming Semiconductor Technologies

(Please see Presentation)

Some Implications brought in by the Coming Semiconductor Technologies 10nm FinFET technologies are ramping up in production, and at the same time, fabs are already introducing 7nm technologies. Looking at the next node, it seems clear the FinFET will remain the prevalent device, and EUV will be used for wafer processing on some layers. We will go over some of the implications, particularly challenges in Physical Design, Design and Technology Co-Optimization, and the use of 2.5 and 3D approaches for integration.

Session 1: Design Acceleration

Naresh Sehgal

Data-center Security Director (bio)

Intel

Session Chair

Rajesh Gupta

Professor (bio)

UCSD

Compositional Synthesis for High-Level Design

(Please see Presentation)

John Lee

General Manager and Vice-President of the Semiconductor Business Unit (bio)

Ansys

Big Data and Machine Learning for Chip Design

(Please see Presentation)

ANSYS has developed an open, extensible and purpose-built platform that provides Big data and machine learning services for chip design. The SeaScape(tm) platform has been commercially deployed at leading semiconductor companies, and supports industry standard formats for layout, parasitics, timing and power-integrity analyses, and vectored simulation data. The talk will show use cases where customers have built apps on this framework.

Dr. CP Hung

Vice President of Corporate R&D (bio)

ASE Group Taiwan

SiP Technology Direction and Design Challenges

(Please see Presentation)

System in Package (SiP) provides the user the great promise to optimize and differentiate their products to meet their system requirements. This talk will review innovations in SiP technologies - Fan-Out and 2.5D, describing how these promises are fulfilled in achieving higher bandwidth, small form factor, increased functionality, mixed nodes, as well as the co-design, so very important in the big data and mobile applications.

Bill Bottoms

Chairman (bio)

Third Millennium Test Solutions

System Level Design and Simulation for Heterogeneous Integration

(Please see Presentation)

Lunch
Keynote:

Zoe Conroy

Director DFT Group and Manufacturing Test (bio)

Cisco

System-level Testing Prompts a Reflection on the EDA to HVM Highway

(Please see Presentation)

Silicon technology continues to steam ahead moving into heterogeneousness and stacking to stay on the Moore’s Law curve. This provides new challenges from design to HVM and requires the continuous collaboration of IC design tool vendors, designers, bring-up teams and manufacturing engineers to ensure highest standards of testability, reliability and quality are attained for today’s and tomorrow’s industry segments. (more)

Session 2: Driving to Higher Yield Herb Reiter
Session Chair

Herb Reiter

President (bio)

EDA 2 ASIC

Session Co-Chair

Ron Leckie

President (bio)

INFRASTRUCTURE Advisors

Session Co-Chair

Keith Arnold

Director, Global Technical Sales (bio)

PDF Solutions

Expanding Die Yield analysis to include IC Package Impact

(Please see Presentation)

Asim Salim

Vice President of Manufacturing (bio)

Open Silicon

High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs

(Please see Presentation)

The manufacturing supply chain ecosystem is facing some unique challenges in addressing the memory requirments for emerging applications where high bandwidth and density, based on real-time random operations are required. High Bandwidth Memory (HBM2) meets these requirements and delivers unprecedented bandwidth, power efficiency and small form factor for applications such as high performance computing, networking, deep learning, virtual reality, gaming, cloud computing and data. (more)

HC Peng

Director of Test Business Development (bio)

Amkor

Multi-Die Production Test Challenges

(Please see Presentation)

Juan Rey

Vice President of Engineering (bio)

Mentor

Design to Manufacturing Considerations in 3D IC Design, Including Design for Test Implications

(Please see Presentation)

Although Logic CMOS 3D adoption has not matched early industry predictions, there has been notable successes. Moreover, multiple companies are now looking at or are prototyping 3D solutions to address several different market areas. Since this is still early times, different technical, as well as business, approaches are being considered. This talk will cover the technical challenges and how those challenges are being addressed by the electronics design and manufacturing community. (more)

Break and Networking
Session 3: Accelerating Debug and Validation at Quality

John Swan

SoC Platform Validation Technologist (bio)

Intel

Session CoChair

Priyadarsan Patra

Lead Principal Technologist and Validation Architect (bio)

Intel

Session CoChair

Gajinder Panesar

Chief Technical Officer (bio)

UltraSoC

System-Wide Visibility in Post-Silicon
to Drive Meaningful Analytics

(Please see Presentation)

Verification tools have progressed to such a level that block-level, unit and sub-systems can be confidently signed-off as operating correctly. However in modern System-on-chips (SoCs) this is not good enough. (more)

Cynthia M. Cook

Software Architect (bio)

Intel

Validation Analytics - Data You Need at the Speed You Need It

(Please see Presentation)

SoC validation is a data generating and gathering process at an extreme scale. Manufacturing, Functional Validation, Electrical Validation, Power Performance Testing (not to mention Software and others) all generate data that could influence decisions the others make. Unfortunately, each discipline’s work and data usually reside in silos. (more)

Al Czamara

Vice President of Engineering and Chief Technical Officer (bio)

Test Evolution

Integrating Pre-Silicon and Post-Silicon Coverage
to Accelerate SOC Validation

(Please see Presentation)

In a typical SOC development project, pre-silicon verification and post-silicon validation teams use different tools and methods to get their jobs done. Pre-silicon tools and methods, which have evolved to keep up with Moore’s law, have not migrated to post-silicon validation teams. (more)

Vikas Kumar

Lead System Validation Engineer (bio)

Intel

Security vs. Debug - Challenges vs. Opportunities

(Please see Presentation)

Security and Debug are essential requirements of a modern platform. However, they are orthogonal. Security, in general, requires that all assets must be protected to fulfill Confidentiality, Integrity and Availability requirements. Whereas, debug needs that platform must be debug-able and provides Controllability, Observability, and Traceability. (more)

Networking, Dinner & Keynote

Jim Hogan

Managing Partner of Vista Ventures (bio)

Vista Ventures

Keynote: The Fourth Industrial Revolution - The Cognitive Age

(Please see Presentation)

At the World Economic Forum in 2016, the concept the Fourth Industrial Revolution was introduced. This session talk outlines the impact that it will have on our lives and introduces The Cognitive Era. Cognitive Science is a diverse field which is unified and motivated by a single basic inquiry: How does my education, career and life change in The Cognitive Era. How do people, animals, or computers ‘think,’ act, and learn? To understand the mind/brain, cognitive science brings together methods and discoveries from neuroscience, psychology, linguistics, philosophy, and data/computer science.


Friday, September 22d, 2017

Day Two: 8:00AM: Breakfast & Networking, then Keynote

Pankaj Mehra

Founder and Chief Executive Officer (bio)

AwarenaaS

8:45AM: Keynote: Data Centric Computer Architecture

(Please see Presentation)

We examine the world of infrastructure (bits, cores, and fabrics) through the lens of data. The talk begins with a survey of data sources, data varieties, and their growth trends. We dig deeper into the lifecycle of data in order to understand the processes by which data is turned into insightful information. The final part of the talk takes a data-centric view of the world and derives a memory-centric computer architecture, in which the primacy of data is reflected in the engineering of infrastructure. (more)

Break
Session 4: Machine Learning in Manufacturing and Design Aparna Dey
Session Chair

Aparna Dey

Technical Marketing Group Director- Standards

Cadence

Session Chair

Paul Franzon

Cirrus Logic Distinguished Professor (bio)

NCSU

Machine Learning for Next Generation EDA

(Please see Presentation)

In this talk, I will share preliminary results for three ongoing projects in applying machine learning to EDA. These projects are being conducted in the scope of the new Center for Advanced Electronics through Machine Learning (CAEML), recently setup between UIUC, Georgia Tech and NCSU. The talk will start with a brief review on machine learning, and work we are performing in accelerating machine learning codes (more)

David White

Senior Group Director R&D (bio)

Cadence

Machine Learning - Design, Development, Augmented Intelligence

(Please see Presentation)

Rob Aitken

R&D Fellow

ARM

Machine Learning in ARM Processor Design

(Please see Presentation)

Jeff Dyck

Vice President of Technical Operations (bio)

Solido Design Automation

Machine Learning for Engineering

(Please see Presentation)

Engineering applications have accuracy, scalability, and verifiability requirements that are not met by traditional machine learning approaches. This talk examines these engineering-specific challenges and effective solutions based on Solido's experience delivering applied machine learning solutions to EDA over the past twelve years.

Abhijit Chatterjee

Professor

Georgia Tech

Machine Learning in Post Silicon Validation of Mixed Signal,
Analog and RF Circuits

(Please see Presentation)

Break
Lunch
PANEL DISCUSSION:
EDA and IC Design and Manufacturing and Test

Herb Reiter

President (bio)

EDA 2 ASIC

Panel Moderator

(Please see Presentation)

Ron Leckie

President (bio)

INFRASTRUCTURE Advisors

Panel Moderator

Javi DeLa Cruz

Vice President of Engineering (bio)

Invensas

Panelist

Dan Leung

Director of Packaging and Assembly (bio)

Open Silicon

Panelist

Keith Arnold

Director, Global Technical Sales (bio)

PDF Solutions

Panelist

Derek Floyd

Director - Business Development (bio)

Advantest

Panelist

Zoe Conroy

Director DFT Group and Manufacturing Test (bio)

Cisco

Panelist

Craig Nishizaki

Sr. Director ATE Development (bio)

NVIDIA

Panelist

Symposium Wrapup Shishpal Rawat
Session Chair

Naresh Sehgal

Data-center Security Director (bio)

Intel

Audience Feedback - Moderator

Shishpal Rawat

President

CEDA

Closing Comments - Plans for EDPS 2018


Please see also the Biographies Page
and Complete Abstracts Page